A reconfigurable circuit such as a PLD (Programmable Logic Device) or an FPGA (Field Programmable Gate Array), which is capable of changing a configuration of a logic circuit, is well known. Generally, changing the logic circuit of the PLD or the FPGA is realized by writing circuit arrangement information stored in a non-volatile memory such as a ROM into a configuration memory which is a volatile memory within the PLD or the FPGA upon an activation. Also, because the information of the configuration memory is cleared upon a power disconnection, the circuit arrangement information stored in the ROM must be written in the configuration memory once again upon the power supply activation. An approach to configuring the logic circuit of a PLD or an FPGA only once in a state in which the power supply is being supplied in this way is referred to as a static reconfiguration. In contrast to this, FPGAs, or the like, that are able to change a configuration of a logic circuit dynamically while the logic circuit is in operation have been developed, and an approach to changing a logic circuit dynamically in this way is referred to as a dynamic reconfiguration.
Also, there are FPGAs capable of rewriting a circuit configuration of a particular region alone rather than the circuit configuration of the entire chip of the FPGA, and this kind of rewriting is referred to as a partial reconfiguration. In particular, changing another circuit configuration without causing the operation of a circuit that is in operation to stop is referred to as a dynamic partial reconfiguration. In a dynamic partial reconfiguration, by rewriting only a partial region of the configuration memory rather than rewriting the entire configuration memory upon the dynamic reconfiguration, it is possible to partially reconfigure an FPGA logic circuit. By employing such a dynamic partial reconfiguration, it is possible to implement a plurality of logic circuits that can be switched time-divisionally in the regions of the FPGA, for example. As a result, it is possible to flexibly realize various functions with few hardware resources while maintaining high speed computational capabilities of the hardware in accordance with intended uses.
However, even when the circuit configuration can be changed in-operation, the time required for changing (rewriting) the circuit configuration is long, and the time is proportional to the size of the logic circuit configuration information written in the configuration memory. Also, if there are many change locations in the circuit configuration, and changes in the circuits are performed independently for each of the change location circuits, a configuration will need to be performed for each change location, and the rewrite time required to complete the reconfiguration of the circuit on the whole will increase. In Japanese Patent Laid-Open No. 2012-234337, a technique for reducing rewrite times, in which processing having a high possibility of being processed next is predicted in image processing, and configuration data for realizing the predicted processing is loaded into high speed configuration memory in advance is disclosed. It is possible to reduce circuit configuration data load times in image processing and it is possible to allow for optimization of image processing speeds by loading into high speed configuration memory in advance.
Also, an image processing apparatus such as an MFP (MULTI FUNCTION PRINTER) is capable of selecting a plurality of jobs (a copy job, a print job, a SEND job, or the like) in accordance with a request from a user. Image processing corresponding to various processing is realized by hardware or software. In order to support function requests from a user, recent MFPs are equipped with large scale hardware for image processing supporting various functions, and it is possible to realize various functions by accepting detailed settings in accordance with various job content. However, function enhancements in the hardware for image processing corresponding to the contents of various jobs leads to cost increases in the hardware for image processing. Also, time is required to perform settings due to the settings for the hardware for image processing corresponding to the various job contents increasing in number. For this reason, the time required until job execution processing is initiated increases. Accordingly, there is a need to realize, by using reconfigurable circuits for an MFP image processing apparatus, a function corresponding to a requested job in a reconfigurable circuit without implementing all functions corresponding to the various job content is such a way that they are always in hardware.
However, there is a problem with the above described conventional technique as recited below. For example, when the reconfiguration technique in the above described conventional technique is applied to an image processing unit of an image processing apparatus, even though it is possible to change the circuit configuration in-operation, the changed processing circuit unit must match the interfaces of the peripheral circuits connected to the processing circuit unit. In particular, the data processing scheme in the interface must match. For example, if only the processing circuit unit by which performance of a rewriting of the circuit configuration is desired is changed, and the processing scheme for the data does not match that of the peripheral circuits, the processing circuit unit for which the rewriting is performed will not be able to operate normally.
A case of rectangle processing wherein the data processing units that the processing circuit unit, for which the rewriting is performed, handles are rectangular data is considered. As a matter of course, for the data units of the peripheral circuits connected to the processing circuit unit must also be handled as the same rectangle data. For example, if the processing circuit unit for which the rewriting is performed is line processing that handles data in a line form, the data processing scheme differs to that of the peripheral circuit connected to the processing circuit unit, and the scheme for transferring the processing data does not match. For this reason, there is a problem in that if a reconfiguration is not performed by determining a range within which it is necessary to perform the change for the circuit for which the rewriting is performed, the reconfigured circuit will not be able to execute correctly.
Furthermore, there is a problem in that for the time that is required for the change of the circuit configuration (the rewriting), if the execution time for rewriting takes longer, the time required to complete the job that the image processing apparatus executes will take that much longer. The time for the change of the circuit configuration is proportional to the size of the configuration data written in the configuration memory in the reconfigurable circuit. Also, if there are many change locations in the circuit configuration, and changes in the circuits are performed independently for each of the change location circuits, a configuration will need to be performed for each change location, and the rewrite time required to complete the reconfiguration of the circuit on the whole will increase. In approaches to optimizing rewrite times of configuration data in conventional techniques, even if the configuration data is loaded in advance, if the processing circuit rewrite count, or the configuration data size is large, the overall rewrite time cannot be shortened.